OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_xecu.v] - Rev 194

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 New directory structure. root 5749d 01h /aemb/trunk/rtl/verilog/aeMB_xecu.v
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.		 sybreon 6051d 06h /aemb/trunk/rtl/verilog/aeMB_xecu.v
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6164d 04h /aemb/trunk/rtl/verilog/aeMB_xecu.v
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6188d 22h /aemb/trunk/rtl/verilog/aeMB_xecu.v
72 Minor code cleanup. sybreon 6214d 03h /aemb/trunk/rtl/verilog/aeMB_xecu.v
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6227d 22h /aemb/trunk/rtl/verilog/aeMB_xecu.v
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6229d 22h /aemb/trunk/rtl/verilog/aeMB_xecu.v
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6234d 03h /aemb/trunk/rtl/verilog/aeMB_xecu.v
53 Added GET/PUT support through a FSL bus. sybreon 6234d 23h /aemb/trunk/rtl/verilog/aeMB_xecu.v
50 Parameterised optional components. sybreon 6236d 06h /aemb/trunk/rtl/verilog/aeMB_xecu.v
45 Minor code cleanup. sybreon 6241d 12h /aemb/trunk/rtl/verilog/aeMB_xecu.v
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6242d 01h /aemb/trunk/rtl/verilog/aeMB_xecu.v
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6242d 17h /aemb/trunk/rtl/verilog/aeMB_xecu.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.