URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk32.v] - Rev 206

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5583d 14h	/aemb/trunk/sim/verilog/edk32.v
163	updated to new iversim compatibility	sybreon	5866d 19h	/aemb/trunk/sim/verilog/edk32.v
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6025d 12h	/aemb/trunk/sim/verilog/edk32.v
79	Modified for AEMB2	sybreon	6038d 08h	/aemb/trunk/sim/verilog/edk32.v
73	Moved simulation kernel into code.	sybreon	6048d 16h	/aemb/trunk/sim/verilog/edk32.v
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6058d 14h	/aemb/trunk/sim/verilog/edk32.v
67	Minor simulation fixes.	sybreon	6060d 13h	/aemb/trunk/sim/verilog/edk32.v
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6064d 11h	/aemb/trunk/sim/verilog/edk32.v
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6065d 09h	/aemb/trunk/sim/verilog/edk32.v
53	Added GET/PUT support through a FSL bus.	sybreon	6069d 12h	/aemb/trunk/sim/verilog/edk32.v
50	Parameterised optional components.	sybreon	6070d 19h	/aemb/trunk/sim/verilog/edk32.v
49	Added random seed for simulation.	sybreon	6073d 22h	/aemb/trunk/sim/verilog/edk32.v
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6076d 14h	/aemb/trunk/sim/verilog/edk32.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6077d 06h	/aemb/trunk/sim/verilog/edk32.v