URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [syn/] [xilinx/] [aes_top_example.ucf] - Rev 11

Rev	Log message	Author	Age	Path
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4624d 23h	/aes_highthroughput_lowarea/trunk/verilog/syn/xilinx/aes_top_example.ucf