URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_dcache_mem_if.v] - Rev 38

Rev	Log message	Author	Age	Path
37	- Add icarus sim test - Adopt consistent naming scheme - Simplify instruction cache	ultra_embedded	3869d 14h	/altor32/trunk/rtl/cpu/altor32_dcache_mem_if.v
36	Various performance improvements and bug fixes.	ultra_embedded	3875d 03h	/altor32/trunk/rtl/cpu/altor32_dcache_mem_if.v
32	Switch memory interfaces to Wishbone (pipelined). Various bug fixes and improvements.	ultra_embedded	3968d 07h	/altor32/trunk/rtl/cpu/altor32_dcache_mem_if.v
30	Fix verilog issues which break in XST.	ultra_embedded	4072d 10h	/altor32/trunk/rtl/cpu/altor32_dcache_mem_if.v
27	Initial drop of AltOR32 v2	ultra_embedded	4073d 07h	/altor32/trunk/rtl/cpu/altor32_dcache_mem_if.v