URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_icache.v] - Rev 45

Rev	Log message	Author	Age	Path
40	- Add support for 2 way instruction cache (not yet enabled) - Bug fixes and tidy up	ultra_embedded	3848d 04h	/altor32/trunk/rtl/cpu/altor32_icache.v
37	- Add icarus sim test - Adopt consistent naming scheme - Simplify instruction cache	ultra_embedded	3862d 08h	/altor32/trunk/rtl/cpu/altor32_icache.v
36	Various performance improvements and bug fixes.	ultra_embedded	3867d 21h	/altor32/trunk/rtl/cpu/altor32_icache.v
32	Switch memory interfaces to Wishbone (pipelined). Various bug fixes and improvements.	ultra_embedded	3961d 01h	/altor32/trunk/rtl/cpu/altor32_icache.v
30	Fix verilog issues which break in XST.	ultra_embedded	4065d 04h	/altor32/trunk/rtl/cpu/altor32_icache.v
27	Initial drop of AltOR32 v2	ultra_embedded	4066d 01h	/altor32/trunk/rtl/cpu/altor32_icache.v