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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_regfile_sim.v] - Rev 34

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32 Switch memory interfaces to Wishbone (pipelined).
Various bug fixes and improvements.
ultra_embedded 3983d 16h /altor32/trunk/rtl/cpu/altor32_regfile_sim.v
27 Initial drop of AltOR32 v2 ultra_embedded 4088d 15h /altor32/trunk/rtl/cpu/altor32_regfile_sim.v

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