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[/] [altor32/] [trunk/] [rtl/] [sim/] [ram.v] - Rev 45

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32 Switch memory interfaces to Wishbone (pipelined).
Various bug fixes and improvements.
ultra_embedded 3961d 03h /altor32/trunk/rtl/sim/ram.v
27 Initial drop of AltOR32 v2 ultra_embedded 4066d 02h /altor32/trunk/rtl/sim/ram.v

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