URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_dcache.v] - Rev 84

Rev	Log message	Author	Age	Path
82	Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug	csantifort	3529d 22h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4216d 10h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4721d 01h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	4921d 00h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4924d 06h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	5013d 04h	/amber/trunk/hw/vlog/amber25/a25_dcache.v
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	5015d 18h	/amber/trunk/hw/vlog/amber25/a25_dcache.v