URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_decode.v] - Rev 67

Rev	Log message	Author	Age	Path
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4221d 08h	/amber/trunk/hw/vlog/amber25/a25_decode.v
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4725d 23h	/amber/trunk/hw/vlog/amber25/a25_decode.v
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4827d 21h	/amber/trunk/hw/vlog/amber25/a25_decode.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4929d 04h	/amber/trunk/hw/vlog/amber25/a25_decode.v
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	5014d 04h	/amber/trunk/hw/vlog/amber25/a25_decode.v
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	5018d 01h	/amber/trunk/hw/vlog/amber25/a25_decode.v
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	5020d 16h	/amber/trunk/hw/vlog/amber25/a25_decode.v