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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_execute.v] - Rev 57

Rev	Log message	Author	Age	Path
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4814d 02h	/amber/trunk/hw/vlog/amber25/a25_execute.v
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4829d 00h	/amber/trunk/hw/vlog/amber25/a25_execute.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4930d 07h	/amber/trunk/hw/vlog/amber25/a25_execute.v
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	5015d 06h	/amber/trunk/hw/vlog/amber25/a25_execute.v
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	5021d 18h	/amber/trunk/hw/vlog/amber25/a25_execute.v