URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [timer_module.v] - Rev 75

Rev	Log message	Author	Age	Path
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4214d 09h	/amber/trunk/hw/vlog/system/timer_module.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4922d 05h	/amber/trunk/hw/vlog/system/timer_module.v
2	Baseline release of the Amber 2 core	csantifort	5044d 02h	/amber/trunk/hw/vlog/system/timer_module.v