URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [uart.v] - Rev 87

Rev	Log message	Author	Age	Path
82	Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug	csantifort	3541d 19h	/amber/trunk/hw/vlog/system/uart.v
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4228d 08h	/amber/trunk/hw/vlog/system/uart.v
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	4900d 01h	/amber/trunk/hw/vlog/system/uart.v
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4936d 04h	/amber/trunk/hw/vlog/system/uart.v
27	Got working with cadence nc simulator	csantifort	4987d 05h	/amber/trunk/hw/vlog/system/uart.v
13	Bug fix - added an extra state to the rx state machine to properly align reading the uart input to the middle of each bit.	csantifort	5029d 04h	/amber/trunk/hw/vlog/system/uart.v
2	Baseline release of the Amber 2 core	csantifort	5058d 02h	/amber/trunk/hw/vlog/system/uart.v