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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-1/] [atahost_top.v] - Rev 33

Rev	Log message	Author	Age	Path
33	New directory structure.	root	5587d 12h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8163d 17h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8165d 20h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8288d 22h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8317d 02h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8322d 22h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8349d 21h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8350d 19h	/ata/trunk/rtl/verilog/ocidec-1/atahost_top.v