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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [axi4-stream-bfm-master.vhdl] - Rev 20

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17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3811d 13h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3914d 10h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
15 [minor]: cleaned up sources. daniel.kho 3916d 16h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3925d 11h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3934d 15h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3936d 10h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3940d 10h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3943d 06h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4043d 12h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4047d 06h /axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl

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