URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] [virtual_jtag_addr_mask.v] - Rev 21

Rev	Log message	Author	Age	Path
15	Released version 2.2.	ash_riple	4476d 12h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4483d 13h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4484d 08h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4489d 08h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4492d 09h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v
2	Checked in working code base.	ash_riple	4496d 08h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_addr_mask.v