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[/] [can/] [tags/] [asyst_2/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5614d 13h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7585d 03h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
130	mbist signals updated according to newest convention	markom	7585d 03h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
129	Error counters changed.	mohor	7601d 12h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7602d 08h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
125	Synchronization changed, error counters fixed.	mohor	7606d 14h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7634d 02h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7675d 18h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
110	Fixed according to the linter.	mohor	7677d 18h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
107	Fixed according to the linter.	mohor	7677d 20h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7684d 07h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7686d 22h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7690d 23h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7696d 12h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7701d 23h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7702d 21h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7706d 18h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7707d 18h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7707d 19h	/can/tags/asyst_2/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7712d 19h	/can/tags/asyst_2/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [asyst_2/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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