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[/] [can/] [tags/] [asyst_2/] [rtl/] [verilog/] [can_btl.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5614d 13h /can/tags/asyst_2/rtl/verilog/can_btl.v
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7585d 03h /can/tags/asyst_2/rtl/verilog/can_btl.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7602d 08h /can/tags/asyst_2/rtl/verilog/can_btl.v
125 Synchronization changed, error counters fixed. mohor 7606d 14h /can/tags/asyst_2/rtl/verilog/can_btl.v
108 Fixed according to the linter. mohor 7677d 19h /can/tags/asyst_2/rtl/verilog/can_btl.v
106 Unused signal removed. mohor 7683d 17h /can/tags/asyst_2/rtl/verilog/can_btl.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7684d 07h /can/tags/asyst_2/rtl/verilog/can_btl.v
102 Little fixes (to fix warnings). mohor 7686d 21h /can/tags/asyst_2/rtl/verilog/can_btl.v
100 Synchronization changed. mohor 7690d 23h /can/tags/asyst_2/rtl/verilog/can_btl.v
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7703d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7703d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7706d 17h /can/tags/asyst_2/rtl/verilog/can_btl.v
82 Removed few signals. mohor 7706d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7707d 19h /can/tags/asyst_2/rtl/verilog/can_btl.v
77 Synchronization is also needed when transmitting a message. mohor 7710d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
76 Counters width changed. mohor 7710d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
75 When switching to tx, sync stage is overjumped. mohor 7712d 18h /can/tags/asyst_2/rtl/verilog/can_btl.v
35 Several registers added. Not finished, yet. mohor 7829d 12h /can/tags/asyst_2/rtl/verilog/can_btl.v
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7834d 14h /can/tags/asyst_2/rtl/verilog/can_btl.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7835d 06h /can/tags/asyst_2/rtl/verilog/can_btl.v

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