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[/] [can/] [tags/] [asyst_2/] [rtl/] [verilog/] [can_defines.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5648d 07h	/can/tags/asyst_2/rtl/verilog/can_defines.v
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7618d 21h	/can/tags/asyst_2/rtl/verilog/can_defines.v
130	mbist signals updated according to newest convention	markom	7618d 21h	/can/tags/asyst_2/rtl/verilog/can_defines.v
124	ALTERA_RAM supported.	mohor	7660d 14h	/can/tags/asyst_2/rtl/verilog/can_defines.v
115	Artisan ram instances added.	simons	7682d 11h	/can/tags/asyst_2/rtl/verilog/can_defines.v
95	Virtual silicon ram instances added.	simons	7730d 06h	/can/tags/asyst_2/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7748d 16h	/can/tags/asyst_2/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7829d 10h	/can/tags/asyst_2/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7837d 23h	/can/tags/asyst_2/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7844d 12h	/can/tags/asyst_2/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7848d 04h	/can/tags/asyst_2/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7869d 01h	/can/tags/asyst_2/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7913d 03h	/can/tags/asyst_2/rtl/verilog/can_defines.v
2	Initial	mohor	7919d 10h	/can/tags/asyst_2/rtl/verilog/can_defines.v