OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [asyst_2/] [rtl/] [verilog/] [can_top.v] - Rev 161

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 New directory structure. root 5648d 07h /can/tags/asyst_2/rtl/verilog/can_top.v
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7618d 21h /can/tags/asyst_2/rtl/verilog/can_top.v
130 mbist signals updated according to newest convention markom 7618d 21h /can/tags/asyst_2/rtl/verilog/can_top.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7636d 02h /can/tags/asyst_2/rtl/verilog/can_top.v
125 Synchronization changed, error counters fixed. mohor 7640d 08h /can/tags/asyst_2/rtl/verilog/can_top.v
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7676d 17h /can/tags/asyst_2/rtl/verilog/can_top.v
110 Fixed according to the linter. mohor 7711d 12h /can/tags/asyst_2/rtl/verilog/can_top.v
106 Unused signal removed. mohor 7717d 12h /can/tags/asyst_2/rtl/verilog/can_top.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7718d 01h /can/tags/asyst_2/rtl/verilog/can_top.v
102 Little fixes (to fix warnings). mohor 7720d 16h /can/tags/asyst_2/rtl/verilog/can_top.v
100 Synchronization changed. mohor 7724d 18h /can/tags/asyst_2/rtl/verilog/can_top.v
95 Virtual silicon ram instances added. simons 7730d 06h /can/tags/asyst_2/rtl/verilog/can_top.v
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.
mohor 7740d 13h /can/tags/asyst_2/rtl/verilog/can_top.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7741d 13h /can/tags/asyst_2/rtl/verilog/can_top.v
77 Synchronization is also needed when transmitting a message. mohor 7744d 12h /can/tags/asyst_2/rtl/verilog/can_top.v
75 When switching to tx, sync stage is overjumped. mohor 7746d 13h /can/tags/asyst_2/rtl/verilog/can_top.v
71 Ports added for the CAN_BIST. mohor 7748d 16h /can/tags/asyst_2/rtl/verilog/can_top.v
67 CAN interrupt is active low. mohor 7823d 16h /can/tags/asyst_2/rtl/verilog/can_top.v
66 unix. mohor 7829d 10h /can/tags/asyst_2/rtl/verilog/can_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.