URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_defines.v] - Rev 163

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5622d 22h	/can/tags/asyst_3/rtl/verilog/can_defines.v
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7593d 12h	/can/tags/asyst_3/rtl/verilog/can_defines.v
130	mbist signals updated according to newest convention	markom	7593d 12h	/can/tags/asyst_3/rtl/verilog/can_defines.v
124	ALTERA_RAM supported.	mohor	7635d 05h	/can/tags/asyst_3/rtl/verilog/can_defines.v
115	Artisan ram instances added.	simons	7657d 02h	/can/tags/asyst_3/rtl/verilog/can_defines.v
95	Virtual silicon ram instances added.	simons	7704d 21h	/can/tags/asyst_3/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7723d 06h	/can/tags/asyst_3/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7804d 01h	/can/tags/asyst_3/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7812d 14h	/can/tags/asyst_3/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7819d 03h	/can/tags/asyst_3/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7822d 19h	/can/tags/asyst_3/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7843d 15h	/can/tags/asyst_3/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7887d 18h	/can/tags/asyst_3/rtl/verilog/can_defines.v
2	Initial	mohor	7894d 01h	/can/tags/asyst_3/rtl/verilog/can_defines.v