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[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_fifo.v] - Rev 163

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Rev Log message Author Age Path
161 New directory structure. root 5622d 22h /can/tags/asyst_3/rtl/verilog/can_fifo.v
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7593d 12h /can/tags/asyst_3/rtl/verilog/can_fifo.v
130 mbist signals updated according to newest convention markom 7593d 12h /can/tags/asyst_3/rtl/verilog/can_fifo.v
124 ALTERA_RAM supported. mohor 7635d 05h /can/tags/asyst_3/rtl/verilog/can_fifo.v
118 Artisan RAM fixed (when not using BIST). mohor 7651d 08h /can/tags/asyst_3/rtl/verilog/can_fifo.v
115 Artisan ram instances added. simons 7657d 02h /can/tags/asyst_3/rtl/verilog/can_fifo.v
109 Fixed according to the linter. mohor 7686d 04h /can/tags/asyst_3/rtl/verilog/can_fifo.v
99 PCI_BIST replaced with CAN_BIST. mohor 7699d 08h /can/tags/asyst_3/rtl/verilog/can_fifo.v
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7704d 20h /can/tags/asyst_3/rtl/verilog/can_fifo.v
95 Virtual silicon ram instances added. simons 7704d 21h /can/tags/asyst_3/rtl/verilog/can_fifo.v
85 Typo fixed. mohor 7713d 19h /can/tags/asyst_3/rtl/verilog/can_fifo.v
73 overrun and length_info fifos are initialized at the end of reset. mohor 7721d 08h /can/tags/asyst_3/rtl/verilog/can_fifo.v
51 Xilinx RAM added. mohor 7819d 03h /can/tags/asyst_3/rtl/verilog/can_fifo.v
48 Actel APA ram supported. mohor 7822d 19h /can/tags/asyst_3/rtl/verilog/can_fifo.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7833d 03h /can/tags/asyst_3/rtl/verilog/can_fifo.v
35 Several registers added. Not finished, yet. mohor 7837d 22h /can/tags/asyst_3/rtl/verilog/can_fifo.v
31 Wishbone interface added. mohor 7841d 17h /can/tags/asyst_3/rtl/verilog/can_fifo.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7843d 15h /can/tags/asyst_3/rtl/verilog/can_fifo.v
24 backup. mohor 7852d 17h /can/tags/asyst_3/rtl/verilog/can_fifo.v
23 Fifo corrected to be synthesizable. mohor 7866d 00h /can/tags/asyst_3/rtl/verilog/can_fifo.v

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