URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_registers.v] - Rev 163

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5622d 22h	/can/tags/asyst_3/rtl/verilog/can_registers.v
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7593d 12h	/can/tags/asyst_3/rtl/verilog/can_registers.v
125	Synchronization changed, error counters fixed.	mohor	7614d 23h	/can/tags/asyst_3/rtl/verilog/can_registers.v
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7686d 03h	/can/tags/asyst_3/rtl/verilog/can_registers.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7692d 16h	/can/tags/asyst_3/rtl/verilog/can_registers.v
102	Little fixes (to fix warnings).	mohor	7695d 07h	/can/tags/asyst_3/rtl/verilog/can_registers.v
93	synthesis full_case parallel_case fixed.	mohor	7710d 08h	/can/tags/asyst_3/rtl/verilog/can_registers.v
92	clkout is clk/2 after the reset.	mohor	7710d 17h	/can/tags/asyst_3/rtl/verilog/can_registers.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7711d 06h	/can/tags/asyst_3/rtl/verilog/can_registers.v
70	data_out is already registered in the can_top.v file.	mohor	7723d 07h	/can/tags/asyst_3/rtl/verilog/can_registers.v
69	Some features are supported in extended mode only (listen_only_mode...).	mohor	7778d 03h	/can/tags/asyst_3/rtl/verilog/can_registers.v
66	unix.	mohor	7804d 01h	/can/tags/asyst_3/rtl/verilog/can_registers.v