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[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_top.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5660d 14h /can/tags/asyst_3/rtl/verilog/can_top.v
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7631d 04h /can/tags/asyst_3/rtl/verilog/can_top.v
130 mbist signals updated according to newest convention markom 7631d 04h /can/tags/asyst_3/rtl/verilog/can_top.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7648d 09h /can/tags/asyst_3/rtl/verilog/can_top.v
125 Synchronization changed, error counters fixed. mohor 7652d 15h /can/tags/asyst_3/rtl/verilog/can_top.v
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7689d 00h /can/tags/asyst_3/rtl/verilog/can_top.v
110 Fixed according to the linter. mohor 7723d 18h /can/tags/asyst_3/rtl/verilog/can_top.v
106 Unused signal removed. mohor 7729d 18h /can/tags/asyst_3/rtl/verilog/can_top.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7730d 08h /can/tags/asyst_3/rtl/verilog/can_top.v
102 Little fixes (to fix warnings). mohor 7732d 22h /can/tags/asyst_3/rtl/verilog/can_top.v
100 Synchronization changed. mohor 7737d 00h /can/tags/asyst_3/rtl/verilog/can_top.v
95 Virtual silicon ram instances added. simons 7742d 13h /can/tags/asyst_3/rtl/verilog/can_top.v
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.
mohor 7752d 19h /can/tags/asyst_3/rtl/verilog/can_top.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7753d 20h /can/tags/asyst_3/rtl/verilog/can_top.v
77 Synchronization is also needed when transmitting a message. mohor 7756d 19h /can/tags/asyst_3/rtl/verilog/can_top.v
75 When switching to tx, sync stage is overjumped. mohor 7758d 19h /can/tags/asyst_3/rtl/verilog/can_top.v
71 Ports added for the CAN_BIST. mohor 7760d 22h /can/tags/asyst_3/rtl/verilog/can_top.v
67 CAN interrupt is active low. mohor 7835d 22h /can/tags/asyst_3/rtl/verilog/can_top.v
66 unix. mohor 7841d 17h /can/tags/asyst_3/rtl/verilog/can_top.v

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