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[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5703d 13h	/can/tags/rel_10/rtl/verilog/can_bsp.v
101	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7780d 00h	/can/tags/rel_10/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7780d 00h	/can/tags/rel_10/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7785d 12h	/can/tags/rel_10/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7790d 23h	/can/tags/rel_10/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7791d 21h	/can/tags/rel_10/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7795d 19h	/can/tags/rel_10/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7796d 19h	/can/tags/rel_10/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7796d 19h	/can/tags/rel_10/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7801d 19h	/can/tags/rel_10/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7903d 10h	/can/tags/rel_10/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7913d 09h	/can/tags/rel_10/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7913d 10h	/can/tags/rel_10/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7913d 18h	/can/tags/rel_10/rtl/verilog/can_bsp.v
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7915d 09h	/can/tags/rel_10/rtl/verilog/can_bsp.v
35	Several registers added. Not finished, yet.	mohor	7918d 13h	/can/tags/rel_10/rtl/verilog/can_bsp.v
32	abort_tx added. Bit destuff fixed.	mohor	7920d 19h	/can/tags/rel_10/rtl/verilog/can_bsp.v
31	Wishbone interface added.	mohor	7922d 08h	/can/tags/rel_10/rtl/verilog/can_bsp.v
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7922d 17h	/can/tags/rel_10/rtl/verilog/can_bsp.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7923d 14h	/can/tags/rel_10/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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