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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5590d 10h	/can/tags/rel_11/rtl/verilog/can_bsp.v
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7660d 04h	/can/tags/rel_11/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7660d 04h	/can/tags/rel_11/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7662d 19h	/can/tags/rel_11/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7666d 20h	/can/tags/rel_11/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7672d 09h	/can/tags/rel_11/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7677d 20h	/can/tags/rel_11/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7678d 18h	/can/tags/rel_11/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7682d 15h	/can/tags/rel_11/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7683d 15h	/can/tags/rel_11/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7683d 16h	/can/tags/rel_11/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7688d 16h	/can/tags/rel_11/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7790d 07h	/can/tags/rel_11/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7800d 06h	/can/tags/rel_11/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7800d 07h	/can/tags/rel_11/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7800d 15h	/can/tags/rel_11/rtl/verilog/can_bsp.v
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7802d 06h	/can/tags/rel_11/rtl/verilog/can_bsp.v
35	Several registers added. Not finished, yet.	mohor	7805d 10h	/can/tags/rel_11/rtl/verilog/can_bsp.v
32	abort_tx added. Bit destuff fixed.	mohor	7807d 16h	/can/tags/rel_11/rtl/verilog/can_bsp.v
31	Wishbone interface added.	mohor	7809d 05h	/can/tags/rel_11/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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