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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 163

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5589d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7659d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
99	PCI_BIST replaced with CAN_BIST.	mohor	7665d 22h	/can/tags/rel_11/rtl/verilog/can_fifo.v
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7671d 09h	/can/tags/rel_11/rtl/verilog/can_fifo.v
95	Virtual silicon ram instances added.	simons	7671d 10h	/can/tags/rel_11/rtl/verilog/can_fifo.v
85	Typo fixed.	mohor	7680d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7687d 21h	/can/tags/rel_11/rtl/verilog/can_fifo.v
51	Xilinx RAM added.	mohor	7785d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
48	Actel APA ram supported.	mohor	7789d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7799d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
35	Several registers added. Not finished, yet.	mohor	7804d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
31	Wishbone interface added.	mohor	7808d 06h	/can/tags/rel_11/rtl/verilog/can_fifo.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7810d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
24	backup.	mohor	7819d 06h	/can/tags/rel_11/rtl/verilog/can_fifo.v
23	Fifo corrected to be synthesizable.	mohor	7832d 13h	/can/tags/rel_11/rtl/verilog/can_fifo.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7834d 18h	/can/tags/rel_11/rtl/verilog/can_fifo.v
17	Addresses corrected to decimal values (previously hex).	mohor	7835d 14h	/can/tags/rel_11/rtl/verilog/can_fifo.v
16	rx_fifo is now working.	mohor	7835d 19h	/can/tags/rel_11/rtl/verilog/can_fifo.v
14	rx fifo added. Not 100 % verified, yet.	mohor	7840d 09h	/can/tags/rel_11/rtl/verilog/can_fifo.v
13	Temporary files (backup).	mohor	7840d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 163

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