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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_top.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5590d 10h	/can/tags/rel_11/rtl/verilog/can_top.v
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7660d 04h	/can/tags/rel_11/rtl/verilog/can_top.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7660d 04h	/can/tags/rel_11/rtl/verilog/can_top.v
102	Little fixes (to fix warnings).	mohor	7662d 19h	/can/tags/rel_11/rtl/verilog/can_top.v
100	Synchronization changed.	mohor	7666d 21h	/can/tags/rel_11/rtl/verilog/can_top.v
95	Virtual silicon ram instances added.	simons	7672d 09h	/can/tags/rel_11/rtl/verilog/can_top.v
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7682d 16h	/can/tags/rel_11/rtl/verilog/can_top.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7683d 16h	/can/tags/rel_11/rtl/verilog/can_top.v
77	Synchronization is also needed when transmitting a message.	mohor	7686d 15h	/can/tags/rel_11/rtl/verilog/can_top.v
75	When switching to tx, sync stage is overjumped.	mohor	7688d 16h	/can/tags/rel_11/rtl/verilog/can_top.v
71	Ports added for the CAN_BIST.	mohor	7690d 19h	/can/tags/rel_11/rtl/verilog/can_top.v
67	CAN interrupt is active low.	mohor	7765d 19h	/can/tags/rel_11/rtl/verilog/can_top.v
66	unix.	mohor	7771d 13h	/can/tags/rel_11/rtl/verilog/can_top.v