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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5639d 18h	/can/tags/rel_16/rtl/verilog/can_bsp.v
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7659d 07h	/can/tags/rel_16/rtl/verilog/can_bsp.v
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7659d 07h	/can/tags/rel_16/rtl/verilog/can_bsp.v
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7700d 22h	/can/tags/rel_16/rtl/verilog/can_bsp.v
110	Fixed according to the linter.	mohor	7702d 23h	/can/tags/rel_16/rtl/verilog/can_bsp.v
107	Fixed according to the linter.	mohor	7703d 00h	/can/tags/rel_16/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7709d 12h	/can/tags/rel_16/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7712d 02h	/can/tags/rel_16/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7716d 04h	/can/tags/rel_16/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7721d 17h	/can/tags/rel_16/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7727d 04h	/can/tags/rel_16/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7728d 01h	/can/tags/rel_16/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7731d 23h	/can/tags/rel_16/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7732d 23h	/can/tags/rel_16/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7733d 00h	/can/tags/rel_16/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7737d 23h	/can/tags/rel_16/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7839d 15h	/can/tags/rel_16/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7849d 13h	/can/tags/rel_16/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7849d 14h	/can/tags/rel_16/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7849d 23h	/can/tags/rel_16/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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