URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5639d 18h	/can/tags/rel_16/rtl/verilog/can_fifo.v
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7659d 07h	/can/tags/rel_16/rtl/verilog/can_fifo.v
118	Artisan RAM fixed (when not using BIST).	mohor	7668d 04h	/can/tags/rel_16/rtl/verilog/can_fifo.v
115	Artisan ram instances added.	simons	7673d 22h	/can/tags/rel_16/rtl/verilog/can_fifo.v
109	Fixed according to the linter.	mohor	7703d 00h	/can/tags/rel_16/rtl/verilog/can_fifo.v
99	PCI_BIST replaced with CAN_BIST.	mohor	7716d 04h	/can/tags/rel_16/rtl/verilog/can_fifo.v
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7721d 15h	/can/tags/rel_16/rtl/verilog/can_fifo.v
95	Virtual silicon ram instances added.	simons	7721d 17h	/can/tags/rel_16/rtl/verilog/can_fifo.v
85	Typo fixed.	mohor	7730d 15h	/can/tags/rel_16/rtl/verilog/can_fifo.v
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7738d 04h	/can/tags/rel_16/rtl/verilog/can_fifo.v
51	Xilinx RAM added.	mohor	7835d 23h	/can/tags/rel_16/rtl/verilog/can_fifo.v
48	Actel APA ram supported.	mohor	7839d 15h	/can/tags/rel_16/rtl/verilog/can_fifo.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7849d 23h	/can/tags/rel_16/rtl/verilog/can_fifo.v
35	Several registers added. Not finished, yet.	mohor	7854d 17h	/can/tags/rel_16/rtl/verilog/can_fifo.v
31	Wishbone interface added.	mohor	7858d 13h	/can/tags/rel_16/rtl/verilog/can_fifo.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7860d 11h	/can/tags/rel_16/rtl/verilog/can_fifo.v
24	backup.	mohor	7869d 12h	/can/tags/rel_16/rtl/verilog/can_fifo.v
23	Fifo corrected to be synthesizable.	mohor	7882d 20h	/can/tags/rel_16/rtl/verilog/can_fifo.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7885d 00h	/can/tags/rel_16/rtl/verilog/can_fifo.v
17	Addresses corrected to decimal values (previously hex).	mohor	7885d 20h	/can/tags/rel_16/rtl/verilog/can_fifo.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories can

[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

Filtering Options