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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_top.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5609d 10h /can/tags/rel_16/rtl/verilog/can_top.v
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7628d 23h /can/tags/rel_16/rtl/verilog/can_top.v
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7637d 20h /can/tags/rel_16/rtl/verilog/can_top.v
110 Fixed according to the linter. mohor 7672d 15h /can/tags/rel_16/rtl/verilog/can_top.v
106 Unused signal removed. mohor 7678d 15h /can/tags/rel_16/rtl/verilog/can_top.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7679d 04h /can/tags/rel_16/rtl/verilog/can_top.v
102 Little fixes (to fix warnings). mohor 7681d 19h /can/tags/rel_16/rtl/verilog/can_top.v
100 Synchronization changed. mohor 7685d 21h /can/tags/rel_16/rtl/verilog/can_top.v
95 Virtual silicon ram instances added. simons 7691d 09h /can/tags/rel_16/rtl/verilog/can_top.v
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7701d 16h /can/tags/rel_16/rtl/verilog/can_top.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7702d 16h /can/tags/rel_16/rtl/verilog/can_top.v
77 Synchronization is also needed when transmitting a message. mohor 7705d 15h /can/tags/rel_16/rtl/verilog/can_top.v
75 When switching to tx, sync stage is overjumped. mohor 7707d 16h /can/tags/rel_16/rtl/verilog/can_top.v
71 Ports added for the CAN_BIST. mohor 7709d 19h /can/tags/rel_16/rtl/verilog/can_top.v
67 CAN interrupt is active low. mohor 7784d 19h /can/tags/rel_16/rtl/verilog/can_top.v
66 unix. mohor 7790d 13h /can/tags/rel_16/rtl/verilog/can_top.v

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