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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_top.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5599d 18h	/can/tags/rel_22/rtl/verilog/can_top.v
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7196d 07h	/can/tags/rel_22/rtl/verilog/can_top.v
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7455d 23h	/can/tags/rel_22/rtl/verilog/can_top.v
130	mbist signals updated according to newest convention	markom	7570d 08h	/can/tags/rel_22/rtl/verilog/can_top.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7587d 13h	/can/tags/rel_22/rtl/verilog/can_top.v
125	Synchronization changed, error counters fixed.	mohor	7591d 19h	/can/tags/rel_22/rtl/verilog/can_top.v
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7628d 04h	/can/tags/rel_22/rtl/verilog/can_top.v
110	Fixed according to the linter.	mohor	7662d 23h	/can/tags/rel_22/rtl/verilog/can_top.v
106	Unused signal removed.	mohor	7668d 22h	/can/tags/rel_22/rtl/verilog/can_top.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7669d 12h	/can/tags/rel_22/rtl/verilog/can_top.v
102	Little fixes (to fix warnings).	mohor	7672d 03h	/can/tags/rel_22/rtl/verilog/can_top.v
100	Synchronization changed.	mohor	7676d 04h	/can/tags/rel_22/rtl/verilog/can_top.v
95	Virtual silicon ram instances added.	simons	7681d 17h	/can/tags/rel_22/rtl/verilog/can_top.v
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7692d 00h	/can/tags/rel_22/rtl/verilog/can_top.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7693d 00h	/can/tags/rel_22/rtl/verilog/can_top.v
77	Synchronization is also needed when transmitting a message.	mohor	7695d 23h	/can/tags/rel_22/rtl/verilog/can_top.v
75	When switching to tx, sync stage is overjumped.	mohor	7698d 00h	/can/tags/rel_22/rtl/verilog/can_top.v
71	Ports added for the CAN_BIST.	mohor	7700d 02h	/can/tags/rel_22/rtl/verilog/can_top.v
67	CAN interrupt is active low.	mohor	7775d 03h	/can/tags/rel_22/rtl/verilog/can_top.v
66	unix.	mohor	7780d 21h	/can/tags/rel_22/rtl/verilog/can_top.v

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_top.v] - Rev 161

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