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[/] [can/] [tags/] [rel_23/] [bench/] [verilog/] [can_testbench_defines.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5607d 17h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7204d 01h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7594d 16h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7819d 12h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7828d 10h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
16	rx_fifo is now working.	mohor	7854d 00h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
13	Temporary files (backup).	mohor	7858d 22h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
11	Acceptance filter added.	mohor	7860d 10h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
10	Backup version.	mohor	7871d 08h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7872d 12h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v
8	Testbench define file added. Clock divider register added.	mohor	7872d 21h	/can/tags/rel_23/bench/verilog/can_testbench_defines.v