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[/] [can/] [tags/] [rel_3/] [rtl/] [verilog/] [can_bsp.v] - Rev 163

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5622d 23h	/can/tags/rel_3/rtl/verilog/can_bsp.v
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7721d 09h	/can/tags/rel_3/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7822d 20h	/can/tags/rel_3/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7832d 18h	/can/tags/rel_3/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7832d 19h	/can/tags/rel_3/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7833d 04h	/can/tags/rel_3/rtl/verilog/can_bsp.v
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7834d 19h	/can/tags/rel_3/rtl/verilog/can_bsp.v
35	Several registers added. Not finished, yet.	mohor	7837d 22h	/can/tags/rel_3/rtl/verilog/can_bsp.v
32	abort_tx added. Bit destuff fixed.	mohor	7840d 04h	/can/tags/rel_3/rtl/verilog/can_bsp.v
31	Wishbone interface added.	mohor	7841d 18h	/can/tags/rel_3/rtl/verilog/can_bsp.v
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7842d 03h	/can/tags/rel_3/rtl/verilog/can_bsp.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7843d 00h	/can/tags/rel_3/rtl/verilog/can_bsp.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7843d 16h	/can/tags/rel_3/rtl/verilog/can_bsp.v
26	Backup.	mohor	7848d 01h	/can/tags/rel_3/rtl/verilog/can_bsp.v
25	* empty log message *	mohor	7848d 04h	/can/tags/rel_3/rtl/verilog/can_bsp.v
24	backup.	mohor	7852d 17h	/can/tags/rel_3/rtl/verilog/can_bsp.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7867d 05h	/can/tags/rel_3/rtl/verilog/can_bsp.v
21	Data is stored to fifo at the end of ack stage.	mohor	7867d 21h	/can/tags/rel_3/rtl/verilog/can_bsp.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7867d 22h	/can/tags/rel_3/rtl/verilog/can_bsp.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7868d 04h	/can/tags/rel_3/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_3/] [rtl/] [verilog/] [can_bsp.v] - Rev 163

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