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[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] [can_defines.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5607d 21h	/can/tags/rel_6/rtl/verilog/can_defines.v
91	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7696d 04h	/can/tags/rel_6/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7708d 05h	/can/tags/rel_6/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7789d 00h	/can/tags/rel_6/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 12h	/can/tags/rel_6/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7804d 01h	/can/tags/rel_6/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7807d 18h	/can/tags/rel_6/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7828d 14h	/can/tags/rel_6/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7872d 16h	/can/tags/rel_6/rtl/verilog/can_defines.v
2	Initial	mohor	7879d 00h	/can/tags/rel_6/rtl/verilog/can_defines.v