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[/] [can/] [tags/] [rel_9/] [rtl/] [verilog/] [can_top.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5633d 07h	/can/tags/rel_9/rtl/verilog/can_top.v
98	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7715d 05h	/can/tags/rel_9/rtl/verilog/can_top.v
95	Virtual silicon ram instances added.	simons	7715d 06h	/can/tags/rel_9/rtl/verilog/can_top.v
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7725d 13h	/can/tags/rel_9/rtl/verilog/can_top.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7726d 13h	/can/tags/rel_9/rtl/verilog/can_top.v
77	Synchronization is also needed when transmitting a message.	mohor	7729d 12h	/can/tags/rel_9/rtl/verilog/can_top.v
75	When switching to tx, sync stage is overjumped.	mohor	7731d 13h	/can/tags/rel_9/rtl/verilog/can_top.v
71	Ports added for the CAN_BIST.	mohor	7733d 15h	/can/tags/rel_9/rtl/verilog/can_top.v
67	CAN interrupt is active low.	mohor	7808d 16h	/can/tags/rel_9/rtl/verilog/can_top.v
66	unix.	mohor	7814d 10h	/can/tags/rel_9/rtl/verilog/can_top.v