OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [bench/] [verilog/] [can_testbench.v] - Rev 161

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 New directory structure. root 5697d 18h /can/trunk/bench/verilog/can_testbench.v
160 New tests for testing the bus-off. igorm 6747d 00h /can/trunk/bench/verilog/can_testbench.v
158 Fixing overrun problems. igorm 7035d 03h /can/trunk/bench/verilog/can_testbench.v
140 I forgot to thange one signal name. igorm 7514d 20h /can/trunk/bench/verilog/can_testbench.v
139 Signal bus_off_on added. igorm 7514d 20h /can/trunk/bench/verilog/can_testbench.v
130 mbist signals updated according to newest convention markom 7668d 08h /can/trunk/bench/verilog/can_testbench.v
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7684d 17h /can/trunk/bench/verilog/can_testbench.v
119 Artisan RAMs added. mohor 7726d 04h /can/trunk/bench/verilog/can_testbench.v
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7789d 22h /can/trunk/bench/verilog/can_testbench.v
68 CAN inturrupt is active low. mohor 7873d 02h /can/trunk/bench/verilog/can_testbench.v
63 ALE changes on negedge of clk. mohor 7884d 18h /can/trunk/bench/verilog/can_testbench.v
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7887d 08h /can/trunk/bench/verilog/can_testbench.v
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7887d 09h /can/trunk/bench/verilog/can_testbench.v
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7887d 09h /can/trunk/bench/verilog/can_testbench.v
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7893d 22h /can/trunk/bench/verilog/can_testbench.v
50 Top level signal names changed. mohor 7893d 23h /can/trunk/bench/verilog/can_testbench.v
48 Actel APA ram supported. mohor 7897d 15h /can/trunk/bench/verilog/can_testbench.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7907d 23h /can/trunk/bench/verilog/can_testbench.v
38 Temporary backup version (still fully operable). mohor 7909d 13h /can/trunk/bench/verilog/can_testbench.v
35 Several registers added. Not finished, yet. mohor 7912d 17h /can/trunk/bench/verilog/can_testbench.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.