URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [bench/] [verilog/] [can_testbench_defines.v] - Rev 162

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5788d 13h	/can/trunk/bench/verilog/can_testbench_defines.v
160	New tests for testing the bus-off.	igorm	6837d 20h	/can/trunk/bench/verilog/can_testbench_defines.v
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7775d 12h	/can/trunk/bench/verilog/can_testbench_defines.v
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	8000d 09h	/can/trunk/bench/verilog/can_testbench_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	8009d 07h	/can/trunk/bench/verilog/can_testbench_defines.v
16	rx_fifo is now working.	mohor	8034d 21h	/can/trunk/bench/verilog/can_testbench_defines.v
13	Temporary files (backup).	mohor	8039d 18h	/can/trunk/bench/verilog/can_testbench_defines.v
11	Acceptance filter added.	mohor	8041d 07h	/can/trunk/bench/verilog/can_testbench_defines.v
10	Backup version.	mohor	8052d 05h	/can/trunk/bench/verilog/can_testbench_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	8053d 09h	/can/trunk/bench/verilog/can_testbench_defines.v
8	Testbench define file added. Clock divider register added.	mohor	8053d 17h	/can/trunk/bench/verilog/can_testbench_defines.v