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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5948d 05h	/can/trunk/rtl/verilog/can_bsp.v
153	Arbitration capture register changed. SW reset (setting the reset_mode bit) doesn't work as HW reset.	igorm	7516d 05h	/can/trunk/rtl/verilog/can_bsp.v
152	Fixes for compatibility after the SW reset.	igorm	7520d 12h	/can/trunk/rtl/verilog/can_bsp.v
151	When CAN was reset by setting the reset_mode signal in mode register, it was possible that CAN was blocked for a short period of time. Problem occured very rarly.	igorm	7523d 06h	/can/trunk/rtl/verilog/can_bsp.v
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7542d 06h	/can/trunk/rtl/verilog/can_bsp.v
145	Arbitration bug fixed.	igorm	7544d 18h	/can/trunk/rtl/verilog/can_bsp.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7710d 08h	/can/trunk/rtl/verilog/can_bsp.v
136	Error counters changed.	mohor	7804d 10h	/can/trunk/rtl/verilog/can_bsp.v
130	mbist signals updated according to newest convention	markom	7918d 19h	/can/trunk/rtl/verilog/can_bsp.v
129	Error counters changed.	mohor	7935d 03h	/can/trunk/rtl/verilog/can_bsp.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7936d 00h	/can/trunk/rtl/verilog/can_bsp.v
125	Synchronization changed, error counters fixed.	mohor	7940d 06h	/can/trunk/rtl/verilog/can_bsp.v
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7967d 17h	/can/trunk/rtl/verilog/can_bsp.v
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	8009d 09h	/can/trunk/rtl/verilog/can_bsp.v
110	Fixed according to the linter.	mohor	8011d 09h	/can/trunk/rtl/verilog/can_bsp.v
107	Fixed according to the linter.	mohor	8011d 11h	/can/trunk/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	8017d 22h	/can/trunk/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	8020d 13h	/can/trunk/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	8024d 15h	/can/trunk/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	8030d 03h	/can/trunk/rtl/verilog/can_bsp.v

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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