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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Rev 162

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Rev Log message Author Age Path
161 New directory structure. root 5788d 13h /can/trunk/rtl/verilog/can_bsp.v
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7356d 14h /can/trunk/rtl/verilog/can_bsp.v
152 Fixes for compatibility after the SW reset. igorm 7360d 20h /can/trunk/rtl/verilog/can_bsp.v
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7363d 15h /can/trunk/rtl/verilog/can_bsp.v
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7382d 14h /can/trunk/rtl/verilog/can_bsp.v
145 Arbitration bug fixed. igorm 7385d 02h /can/trunk/rtl/verilog/can_bsp.v
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7550d 17h /can/trunk/rtl/verilog/can_bsp.v
136 Error counters changed. mohor 7644d 19h /can/trunk/rtl/verilog/can_bsp.v
130 mbist signals updated according to newest convention markom 7759d 03h /can/trunk/rtl/verilog/can_bsp.v
129 Error counters changed. mohor 7775d 12h /can/trunk/rtl/verilog/can_bsp.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7776d 08h /can/trunk/rtl/verilog/can_bsp.v
125 Synchronization changed, error counters fixed. mohor 7780d 14h /can/trunk/rtl/verilog/can_bsp.v
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7808d 02h /can/trunk/rtl/verilog/can_bsp.v
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7849d 18h /can/trunk/rtl/verilog/can_bsp.v
110 Fixed according to the linter. mohor 7851d 18h /can/trunk/rtl/verilog/can_bsp.v
107 Fixed according to the linter. mohor 7851d 20h /can/trunk/rtl/verilog/can_bsp.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7858d 07h /can/trunk/rtl/verilog/can_bsp.v
102 Little fixes (to fix warnings). mohor 7860d 22h /can/trunk/rtl/verilog/can_bsp.v
100 Synchronization changed. mohor 7864d 23h /can/trunk/rtl/verilog/can_bsp.v
95 Virtual silicon ram instances added. simons 7870d 12h /can/trunk/rtl/verilog/can_bsp.v

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