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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5563d 20h	/can/trunk/rtl/verilog/can_btl.v
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7157d 20h	/can/trunk/rtl/verilog/can_btl.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7325d 23h	/can/trunk/rtl/verilog/can_btl.v
137	Header changed.	mohor	7420d 01h	/can/trunk/rtl/verilog/can_btl.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7551d 14h	/can/trunk/rtl/verilog/can_btl.v
125	Synchronization changed, error counters fixed.	mohor	7555d 20h	/can/trunk/rtl/verilog/can_btl.v
108	Fixed according to the linter.	mohor	7627d 02h	/can/trunk/rtl/verilog/can_btl.v
106	Unused signal removed.	mohor	7633d 00h	/can/trunk/rtl/verilog/can_btl.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7633d 13h	/can/trunk/rtl/verilog/can_btl.v
102	Little fixes (to fix warnings).	mohor	7636d 04h	/can/trunk/rtl/verilog/can_btl.v
100	Synchronization changed.	mohor	7640d 06h	/can/trunk/rtl/verilog/can_btl.v
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7653d 00h	/can/trunk/rtl/verilog/can_btl.v
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7653d 01h	/can/trunk/rtl/verilog/can_btl.v
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7655d 23h	/can/trunk/rtl/verilog/can_btl.v
82	Removed few signals.	mohor	7656d 01h	/can/trunk/rtl/verilog/can_btl.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7657d 01h	/can/trunk/rtl/verilog/can_btl.v
77	Synchronization is also needed when transmitting a message.	mohor	7660d 00h	/can/trunk/rtl/verilog/can_btl.v
76	Counters width changed.	mohor	7660d 00h	/can/trunk/rtl/verilog/can_btl.v
75	When switching to tx, sync stage is overjumped.	mohor	7662d 01h	/can/trunk/rtl/verilog/can_btl.v
35	Several registers added. Not finished, yet.	mohor	7778d 19h	/can/trunk/rtl/verilog/can_btl.v

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Rev 161

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