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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Rev 162

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5788d 13h	/can/trunk/rtl/verilog/can_btl.v
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7382d 14h	/can/trunk/rtl/verilog/can_btl.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7550d 17h	/can/trunk/rtl/verilog/can_btl.v
137	Header changed.	mohor	7644d 18h	/can/trunk/rtl/verilog/can_btl.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7776d 08h	/can/trunk/rtl/verilog/can_btl.v
125	Synchronization changed, error counters fixed.	mohor	7780d 14h	/can/trunk/rtl/verilog/can_btl.v
108	Fixed according to the linter.	mohor	7851d 19h	/can/trunk/rtl/verilog/can_btl.v
106	Unused signal removed.	mohor	7857d 17h	/can/trunk/rtl/verilog/can_btl.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7858d 07h	/can/trunk/rtl/verilog/can_btl.v
102	Little fixes (to fix warnings).	mohor	7860d 22h	/can/trunk/rtl/verilog/can_btl.v
100	Synchronization changed.	mohor	7864d 23h	/can/trunk/rtl/verilog/can_btl.v
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7877d 18h	/can/trunk/rtl/verilog/can_btl.v
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7877d 19h	/can/trunk/rtl/verilog/can_btl.v
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7880d 17h	/can/trunk/rtl/verilog/can_btl.v
82	Removed few signals.	mohor	7880d 18h	/can/trunk/rtl/verilog/can_btl.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7881d 19h	/can/trunk/rtl/verilog/can_btl.v
77	Synchronization is also needed when transmitting a message.	mohor	7884d 18h	/can/trunk/rtl/verilog/can_btl.v
76	Counters width changed.	mohor	7884d 18h	/can/trunk/rtl/verilog/can_btl.v
75	When switching to tx, sync stage is overjumped.	mohor	7886d 19h	/can/trunk/rtl/verilog/can_btl.v
35	Several registers added. Not finished, yet.	mohor	8003d 13h	/can/trunk/rtl/verilog/can_btl.v

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Rev 162

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