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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5572d 17h /can/trunk/rtl/verilog/can_fifo.v
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 7033d 04h /can/trunk/rtl/verilog/can_fifo.v
152 Fixes for compatibility after the SW reset. igorm 7145d 00h /can/trunk/rtl/verilog/can_fifo.v
137 Header changed. mohor 7428d 22h /can/trunk/rtl/verilog/can_fifo.v
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7536d 20h /can/trunk/rtl/verilog/can_fifo.v
130 mbist signals updated according to newest convention markom 7543d 07h /can/trunk/rtl/verilog/can_fifo.v
124 ALTERA_RAM supported. mohor 7585d 00h /can/trunk/rtl/verilog/can_fifo.v
118 Artisan RAM fixed (when not using BIST). mohor 7601d 02h /can/trunk/rtl/verilog/can_fifo.v
115 Artisan ram instances added. simons 7606d 20h /can/trunk/rtl/verilog/can_fifo.v
109 Fixed according to the linter. mohor 7635d 22h /can/trunk/rtl/verilog/can_fifo.v
99 PCI_BIST replaced with CAN_BIST. mohor 7649d 03h /can/trunk/rtl/verilog/can_fifo.v
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7654d 14h /can/trunk/rtl/verilog/can_fifo.v
95 Virtual silicon ram instances added. simons 7654d 16h /can/trunk/rtl/verilog/can_fifo.v
85 Typo fixed. mohor 7663d 13h /can/trunk/rtl/verilog/can_fifo.v
73 overrun and length_info fifos are initialized at the end of reset. mohor 7671d 03h /can/trunk/rtl/verilog/can_fifo.v
51 Xilinx RAM added. mohor 7768d 21h /can/trunk/rtl/verilog/can_fifo.v
48 Actel APA ram supported. mohor 7772d 13h /can/trunk/rtl/verilog/can_fifo.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7782d 22h /can/trunk/rtl/verilog/can_fifo.v
35 Several registers added. Not finished, yet. mohor 7787d 16h /can/trunk/rtl/verilog/can_fifo.v
31 Wishbone interface added. mohor 7791d 11h /can/trunk/rtl/verilog/can_fifo.v

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