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[/] [can/] [trunk/] [rtl/] [verilog/] [can_registers.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5572d 16h /can/trunk/rtl/verilog/can_registers.v
156 Wake-up interrupt was generated in some cases. igorm 7024d 20h /can/trunk/rtl/verilog/can_registers.v
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7132d 20h /can/trunk/rtl/verilog/can_registers.v
152 Fixes for compatibility after the SW reset. igorm 7144d 23h /can/trunk/rtl/verilog/can_registers.v
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7169d 00h /can/trunk/rtl/verilog/can_registers.v
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7334d 20h /can/trunk/rtl/verilog/can_registers.v
125 Synchronization changed, error counters fixed. mohor 7564d 17h /can/trunk/rtl/verilog/can_registers.v
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7635d 20h /can/trunk/rtl/verilog/can_registers.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7642d 10h /can/trunk/rtl/verilog/can_registers.v
102 Little fixes (to fix warnings). mohor 7645d 00h /can/trunk/rtl/verilog/can_registers.v
93 synthesis full_case parallel_case fixed. mohor 7660d 02h /can/trunk/rtl/verilog/can_registers.v
92 clkout is clk/2 after the reset. mohor 7660d 10h /can/trunk/rtl/verilog/can_registers.v
90 paralel_case and full_case compiler directives added to case statements. mohor 7660d 23h /can/trunk/rtl/verilog/can_registers.v
70 data_out is already registered in the can_top.v file. mohor 7673d 00h /can/trunk/rtl/verilog/can_registers.v
69 Some features are supported in extended mode only (listen_only_mode...). mohor 7727d 20h /can/trunk/rtl/verilog/can_registers.v
66 unix. mohor 7753d 19h /can/trunk/rtl/verilog/can_registers.v

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