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[/] [can/] [trunk/] [rtl/] [verilog/] [can_top.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5572d 10h /can/trunk/rtl/verilog/can_top.v
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7168d 18h /can/trunk/rtl/verilog/can_top.v
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7428d 15h /can/trunk/rtl/verilog/can_top.v
130 mbist signals updated according to newest convention markom 7543d 00h /can/trunk/rtl/verilog/can_top.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7560d 05h /can/trunk/rtl/verilog/can_top.v
125 Synchronization changed, error counters fixed. mohor 7564d 11h /can/trunk/rtl/verilog/can_top.v
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7600d 20h /can/trunk/rtl/verilog/can_top.v
110 Fixed according to the linter. mohor 7635d 14h /can/trunk/rtl/verilog/can_top.v
106 Unused signal removed. mohor 7641d 14h /can/trunk/rtl/verilog/can_top.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7642d 04h /can/trunk/rtl/verilog/can_top.v
102 Little fixes (to fix warnings). mohor 7644d 18h /can/trunk/rtl/verilog/can_top.v
100 Synchronization changed. mohor 7648d 20h /can/trunk/rtl/verilog/can_top.v
95 Virtual silicon ram instances added. simons 7654d 09h /can/trunk/rtl/verilog/can_top.v
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7664d 15h /can/trunk/rtl/verilog/can_top.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7665d 16h /can/trunk/rtl/verilog/can_top.v
77 Synchronization is also needed when transmitting a message. mohor 7668d 15h /can/trunk/rtl/verilog/can_top.v
75 When switching to tx, sync stage is overjumped. mohor 7670d 15h /can/trunk/rtl/verilog/can_top.v
71 Ports added for the CAN_BIST. mohor 7672d 18h /can/trunk/rtl/verilog/can_top.v
67 CAN interrupt is active low. mohor 7747d 18h /can/trunk/rtl/verilog/can_top.v
66 unix. mohor 7753d 13h /can/trunk/rtl/verilog/can_top.v

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