URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [trunk/] [sim/] [rtl_sim/] [run/] [run_sim.scr] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5787d 19h	/can/trunk/sim/rtl_sim/run/run_sim.scr
159	* empty log message *	igorm	7125d 02h	/can/trunk/sim/rtl_sim/run/run_sim.scr
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7549d 23h	/can/trunk/sim/rtl_sim/run/run_sim.scr
119	Artisan RAMs added.	mohor	7816d 05h	/can/trunk/sim/rtl_sim/run/run_sim.scr
48	Actel APA ram supported.	mohor	7987d 16h	/can/trunk/sim/rtl_sim/run/run_sim.scr
2	Initial	mohor	8058d 22h	/can/trunk/sim/rtl_sim/run/run_sim.scr