URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [branches/] [avendor/] [rtl/] [vhdl/] [reg_sp.vhd] - Rev 18

Rev	Log message	Author	Age	Path
18	New directory structure.	root	5729d 14h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/reg_sp.vhd
8	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead of $02FF and $0300)	fpga_is_funny	5793d 12h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/reg_sp.vhd
6	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP "JMP (indirect)" produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead $02FF and $0300)	fpga_is_funny	5793d 12h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/reg_sp.vhd
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	6064d 14h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/reg_sp.vhd