URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [branches/] [avendor/] [rtl/] [vhdl/] [testbench.vhd] - Rev 18

Rev	Log message	Author	Age	Path
18	New directory structure.	root	5729d 14h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/testbench.vhd
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	6064d 14h	/cpu6502_true_cycle/branches/avendor/rtl/vhdl/testbench.vhd