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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Rev 26

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26 v1.4 PRODUCTION fpga_is_funny 2262d 08h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
24 Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
simulation with RTI and in a real environment by customer.
Removed directory ./verilog_TRIAL from source.		 fpga_is_funny 5368d 07h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
18 New directory structure. root 5739d 09h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
15 CORRECTED "RTI" (wrong: use of stack pointer)
RENAME all states of "FSM Execution Unit" for better reading
(90%) Finish working for Specification of cpu6502_tc		 fpga_is_funny 5751d 11h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
14 More optimizations...
- Second Phaze of removing unused nets & registers
- Added Verilog source on demand by some customers (for trial use)		 fpga_is_funny 5798d 08h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
11 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads
from $02FF and $0200, instead of $02FF and $0300)		 fpga_is_funny 5803d 07h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
5 Bugfixes for all relationchips with interrupts BRK, IRQ and NMI.
The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down.
The "B" status flag was never set within BRK.
The relationchip between addresses and data while writing onto the stack was badly misalligned.		 fpga_is_funny 6065d 10h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 6074d 09h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
2 First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.		 fpga_is_funny 6074d 09h /cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd

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