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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_cpu.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5620d 00h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
153	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7417d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
152	CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last check-in.	igorm	7417d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
150	Zero is shifted out when CTRL_READ command is active.	igorm	7418d 00h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
143	Signals for easier debugging removed.	igorm	7424d 09h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7425d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
139	New release of the debug interface (3rd. release).	igorm	7427d 23h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
123	All flipflops are reset.	mohor	7491d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
121	Port signals are all set to zero after reset.	mohor	7494d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7497d 12h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7499d 01h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
102	New version.	mohor	7499d 01h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
101	Almost finished.	mohor	7499d 02h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
100	* empty log message *	mohor	7500d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v

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