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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_cpu.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5649d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
153	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7446d 10h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
152	CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last check-in.	igorm	7446d 10h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
150	Zero is shifted out when CTRL_READ command is active.	igorm	7447d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
143	Signals for easier debugging removed.	igorm	7453d 14h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7454d 10h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
139	New release of the debug interface (3rd. release).	igorm	7457d 04h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
123	All flipflops are reset.	mohor	7520d 11h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
121	Port signals are all set to zero after reset.	mohor	7523d 11h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7526d 17h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7528d 06h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
102	New version.	mohor	7528d 07h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
101	Almost finished.	mohor	7528d 08h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v
100	* empty log message *	mohor	7529d 10h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu.v

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