URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5597d 06h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
153	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7394d 11h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
147	CPU_WR_CTRL and CPU_RD_CTRL defines changed.	igorm	7397d 12h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7402d 11h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
139	New release of the debug interface (3rd. release).	igorm	7405d 05h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
138	Temp version before changing dbg interface.	igorm	7411d 09h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
101	Almost finished.	mohor	7476d 09h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v
100	* empty log message *	mohor	7477d 11h	/dbg_interface/tags/asyst_2/rtl/verilog/dbg_cpu_defines.v